x86: fix feature availability for PV guests

PV guests should not be allowed to believe features not currently
virtualized (in many cases, requiring special MSRs) are available. Of
course it is bad enough that to work on older hypervisors guests will
still need to special case this, but better fix it now than never.

Signed-off-by: Jan Beulich <jbeulich@novell.com>

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 90cad362969186fe1bdd3835109ba9f17e3dfa57..019e3e56cfc2209f98c2816b4607f7e4042ab1b6 100644 (file)
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -677,32 +677,75 @@ static int emulate_forced_invalid_op(struct cpu_user_regs *regs)
         : "=a" (a), "=b" (b), "=c" (c), "=d" (d)
         : "0" (a), "1" (b), "2" (c), "3" (d) );
 
-    if ( regs->eax == 1 )
+    if ( (regs->eax & 0x7fffffff) == 1 )
     {
         /* Modify Feature Information. */
         __clear_bit(X86_FEATURE_VME, &d);
         __clear_bit(X86_FEATURE_PSE, &d);
         __clear_bit(X86_FEATURE_PGE, &d);
+        __clear_bit(X86_FEATURE_MCE, &d);
+        __clear_bit(X86_FEATURE_MCA, &d);
+        if ( !IS_PRIV(current->domain) )
+            __clear_bit(X86_FEATURE_MTRR, &d);
+        __clear_bit(X86_FEATURE_PSE36, &d);
+    }
+    switch ( (uint32_t)regs->eax )
+    {
+    case 1:
+        /* Modify Feature Information. */
         if ( !cpu_has_sep )
             __clear_bit(X86_FEATURE_SEP, &d);
 #ifdef __i386__
         if ( !supervisor_mode_kernel )
             __clear_bit(X86_FEATURE_SEP, &d);
 #endif
-        if ( !IS_PRIV(current->domain) )
-            __clear_bit(X86_FEATURE_MTRR, &d);
-    }
-    else if ( regs->eax == 0x80000001 )
-    {
+        __clear_bit(X86_FEATURE_DS, &d);
+        __clear_bit(X86_FEATURE_ACC, &d);
+        __clear_bit(X86_FEATURE_PBE, &d);
+
+        __clear_bit(X86_FEATURE_DTES64 % 32, &c);
+        __clear_bit(X86_FEATURE_MWAIT % 32, &c);
+        __clear_bit(X86_FEATURE_DSCPL % 32, &c);
+        __clear_bit(X86_FEATURE_VMXE % 32, &c);
+        __clear_bit(X86_FEATURE_SMXE % 32, &c);
+        __clear_bit(X86_FEATURE_EST % 32, &c);
+        __clear_bit(X86_FEATURE_TM2 % 32, &c);
+        if ( is_pv_32bit_vcpu(current) )
+            __clear_bit(X86_FEATURE_CX16 % 32, &c);
+        __clear_bit(X86_FEATURE_XTPR % 32, &c);
+        __clear_bit(X86_FEATURE_PDCM % 32, &c);
+        __clear_bit(X86_FEATURE_DCA % 32, &c);
+        break;
+    case 0x80000001:
         /* Modify Feature Information. */
-#ifdef __i386__
-        __clear_bit(X86_FEATURE_SYSCALL % 32, &d);
+        if ( is_pv_32bit_vcpu(current) )
+        {
+            __clear_bit(X86_FEATURE_LM % 32, &d);
+            __clear_bit(X86_FEATURE_LAHF_LM % 32, &c);
+        }
+#ifndef __i386__
+        if ( is_pv_32on64_vcpu(current) &&
+             boot_cpu_data.x86_vendor != X86_VENDOR_AMD )
 #endif
+            __clear_bit(X86_FEATURE_SYSCALL % 32, &d);
+        __clear_bit(X86_FEATURE_PAGE1GB % 32, &d);
         __clear_bit(X86_FEATURE_RDTSCP % 32, &d);
-    }
-    else
-    {
+
+        __clear_bit(X86_FEATURE_SVME % 32, &c);
+        __clear_bit(X86_FEATURE_OSVW % 32, &c);
+        __clear_bit(X86_FEATURE_IBS % 32, &c);
+        __clear_bit(X86_FEATURE_SKINIT % 32, &c);
+        __clear_bit(X86_FEATURE_WDT % 32, &c);
+        break;
+    case 5: /* MONITOR/MWAIT */
+    case 0xa: /* Architectural Performance Monitor Features */
+    case 0x8000000a: /* SVM revision and features */
+    case 0x8000001b: /* Instruction Based Sampling */
+        a = b = c = d = 0;
+        break;
+    default:
         (void)cpuid_hypervisor_leaves(regs->eax, &a, &b, &c, &d);
+        break;
     }
 
     regs->eax = a;
@@ -2035,6 +2078,15 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
             if ( rdmsr_safe(regs->ecx, regs->eax, regs->edx) )
                 goto fail;
             break;
+        case MSR_IA32_MISC_ENABLE:
+            if ( rdmsr_safe(regs->ecx, regs->eax, regs->edx) )
+                goto fail;
+            regs->eax &= ~(MSR_IA32_MISC_ENABLE_PERF_AVAIL |
+                           MSR_IA32_MISC_ENABLE_MONITOR_ENABLE);
+            regs->eax |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL |
+                         MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |
+                         MSR_IA32_MISC_ENABLE_XTPR_DISABLE;
+            break;
         default:
             if ( rdmsr_hypervisor_regs(regs->ecx, &l, &h) )
             {

diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 58c1f9e41f5a914b377a73f86a559e812c0cb4c3..2a164844a235931d0be90293d51105476d7def22 100644 (file)
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -42,6 +42,7 @@
 #define X86_FEATURE_HT         (0*32+28) /* Hyper-Threading */
 #define X86_FEATURE_ACC                (0*32+29) /* Automatic clock control */
 #define X86_FEATURE_IA64       (0*32+30) /* IA-64 processor */
+#define X86_FEATURE_PBE                (0*32+31) /* Pending Break Enable */
 
 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
 /* Don't duplicate feature flags which are redundant with Intel! */
@@ -76,6 +77,7 @@
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3       (4*32+ 0) /* Streaming SIMD Extensions-3 */
+#define X86_FEATURE_DTES64     (4*32+ 2) /* 64-bit Debug Store */
 #define X86_FEATURE_MWAIT      (4*32+ 3) /* Monitor/Mwait support */
 #define X86_FEATURE_DSCPL      (4*32+ 4) /* CPL Qualified Debug Store */
 #define X86_FEATURE_VMXE       (4*32+ 5) /* Virtual Machine Extensions */
@@ -115,6 +117,8 @@
 #define X86_FEATURE_MISALIGNSSE        (6*32+ 7) /* Misaligned SSE Access */
 #define X86_FEATURE_3DNOWPF    (6*32+ 8) /* 3DNow! Prefetch */
 #define X86_FEATURE_OSVW       (6*32+ 9) /* OS Visible Workaround */
+#define X86_FEATURE_IBS                (6*32+ 10) /* Instruction Based Sampling */
+#define X86_FEATURE_SSE5       (6*32+ 11) /* AMD Streaming SIMD Extensions-5 */
 #define X86_FEATURE_SKINIT     (6*32+ 12) /* SKINIT, STGI/CLGI, DEV */
 #define X86_FEATURE_WDT                (6*32+ 13) /* Watchdog Timer */
 

diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 9b1753755d73f0def3fcee4f0906dd9f26f2199e..455075f1965cabcbbfe3936168a9410441ac0cb7 100644 (file)
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -255,6 +255,8 @@
 #define MSR_IA32_MISC_ENABLE_PERF_AVAIL   (1<<7)
 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL  (1<<11)
 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
+#define MSR_IA32_MISC_ENABLE_MONITOR_ENABLE (1<<18)
+#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1<<23)
 
 /* Intel Model 6 */
 #define MSR_P6_EVNTSEL0                        0x00000186